Si comunica che nell’ambito del corso “Design for Testability and Reliability of Integrated Circuits M”
il Dr. Eng. Michael Spica, Cypress Semiconductor (Seattle, USA) , terrà una serie di seminari sul tema:

“Common Industry Applications of DFT/DFM and Relationship to Guard Bands for Reliability in Nanometer Geometry Electronics”

I seminari avranno luogo:

lunedì 6 giugno, ore 10-11, aula 2.6
martedì 7 giugno, ore 9-11, aula 4.1
giovedì 9 giugno, ore 9-12 aula 5.4

Tutti gli interessati sono invitati a partecipare.

Cordiali saluti,

Cecilia Metra

==========================================

Title: Common Industry Applications of DFT/DFM and Relationship to Guard Bands for Reliability in Nanometer Geometry Electronics.

Abstract: The purpose of testing must encompass several disciplines to be comprehensive and sufficient to meet the customer
demands for quality, reliability, and achievement of the design to the manufacturing capabilities. Multiple statistical methods
must be employed to properly analyze and achieve these goals. In addition, multiple inter-disciplinary perspectives of the units
must be sufficiently comprehended to create meaningful test limits that comprise the final test set evaluation for production.
These disciplines include: metrology evaluation, the expectation for predictive device behavior related to degradation, the
expectation of the performance of the device, and the nature of the defects that are to be screened in manufacturing test.
The concept of ‘intrinsic’ vs. ‘extrinsic’ defects must be considered in targeting the final test coverage to guarantee a reasonable
level of quality and this will assess the cost associated with the testing.

Bio: Michael Spica is currently the head of the DFT/DFM Center of Excellence for Cypress Semiconductor after rejoining Cypress
in 2007. In this role he is responsible for establishing the DFT/DFM methodology for the company’s product portfolio which
includes the PSoC devices, high speed USB PHY devices, specialized memories (SRAM and non-volatile SRAM), clocks, and
optical sensors. This incorporates the logical and analog capabilities of all of the devices including the mixed signal and high performance analog testing to be done utilizing multiple BIST as well as other test techniques depending on the tester economics.
Prior to this Michael was a Test Technologist (Product Design Engineer) at Intel Corp. from 1998 through 2007 and was primarily
responsible for process pathfinding issues related to test as well as revisions of the ATE architecture and memory related BIST
architectures working several products from microprocessors in both the consumer and server segments to communications
products. In addition he worked extensively on the erratic bit problems seen in nanometer technologies and methods to resolve
the testability issues. In addition was responsible for modeling the burn-in stress mechanisms and population analysis as well as
redundancy and repair calculation methodology.
>From 1996-1998 Michael was at Cypress Semiconductor and was responsible for 6″ and 8″ wafer and line yield analysis as well as parametric test development (e-test). In addition to performing direct physical failure analysis and process technology
development and evaluation, he was also responsible for developing SPC and DOE methods and analysis to maintain the fab
operations.From 1994-1996 Michael was a test development engineer for Micron Semiconductor working on DRAM memory test methods and incorporation of multi-site testing as well as in-line characterization being done on the ATE. This required modification of the load boards as well as significant coding modifications to the ATE.

Michael graduated with a BSEE/BME (Bachelor of Science Electrical/Biomedical Engineering) from Michigan State University in 1993. He has also attended graduate course work from Utah State University in Device Physics as well as the University of Minnesota.

seminario

In contemporanea con Smau Business, alla Fiera di Bologna (padiglioni 33 e 34), l’8 e il 9 giugno si terrà la fiera dell’innovazione nelle imprese R2B (http://www.rdueb.it/rdueb11/).
In questo contesto sarà possibile scegliere tra varie aree tematiche e partecipare a convegni e Workshop sui temi dell’innovazione.

Tra le iniziative speciali vi segnalo lo Start2B (http://www.rdueb.it/rdueb11/mini_home/channel/start2b/), l’area espositiva di Research to Business dedicata alla presentazione delle start up Emiliano Romagnole.

Tutti gli interessati possono accedere alla fiera gratuitamente stampando l’invito.

Grazie per l’attenzione.
Cordiali saluti,
Sara Bartolini

bologna · business · fiera · research

AVVISO DI SEMINARIO

Mercoledì 11 maggio, alle 14.30, in aula Vitali presso il Dipartimento di Matematica (P.ta San Donato, Bologna), il Prof. Louis H. Kauffman dell’Università dell’Illinois a Chicago terrà un seminario
intitolato:

Virtual Knot Theory and the Jones Polynomial

Abstract:
This talk will show how a natural extension of the Jones polynomial to
knots in thickened surfaces leads to new invariants and the concept of
virtual knot theory.

Organizzato da Massimo Ferri sotto il patrocinio dell’ARCES “E. De Castro”, Univ. di Bologna.

seminario

Graphene has appealing physical properties for electronic applications
like large carrier mobility,
which has triggered an important collective effort aimed at a good
understanding of its electrical behaviour.
Still, from an engineering point of view, the main question to be
answered is:
“Will graphene be capable in the mid term to meet Semiconductor Industry
requirements to keep the pace of Moore’s law?”.

The investigation of graphene-based devices is an open issue due to the
many fabrications problems which remain unsolved.
In this respect, numerical simulations can represent a powerful tool in
order to assess the potential performance of graphene devices.

In this talk, we will present a simulation study to investigate the
limits and the perspectives of graphene devices,
considering a wide span of devices, ranging from graphene nanoribbons
(GNR) to monolayer and bilayer graphene Field Effect Transistors.

seminario

Nell’ambito delle attività previste dall’insegnamento “Trends in
Electronics”, mercoledi 4 e giovedì 5 maggio il Prof. Arokia Nathan del London
Center for Nanotechnology terrà un seminario dal titolo “Large Area
Electronics”.
Siete naturalmente tutti invitati a partecipare.

L’appuntamento per domani è in aula 5.5 (anziché in Sala Consiglio come da
avvisi precedenti) alle ore 16.

seminario

seminario

linux · meego · mobile · open-source

Il centro di Calcolo di Ingegneria e’  allagato, le sedi di via Risorgimento e di viale Pepoli sono isolate.
Per quanto possibile, stiamo cercando di ripristinare parte del lavoro che puo’ essere svolto in locale in entrambe le sedi.

Si auspica che la situazione possa tornare alla normalita’ entro domani.

No tags

Per leggere i contenuti della Riforma Gelmini fare riferimento al link sottostante:

Riforma Gelmini

Gelmini · legge · riforma

Si comunica che in data odierna sono stati aggiornati i certificati di Alfresco, per far fronte ai requisiti di un nuovo strumento che ne migliora le prestazioni.
La scadenza e’ estesa fino al 2020.
Per le modalità di utilizzo del servizio e per una panoramica del sito è vivamente consigliato consultare il Manuale Utente. Nel manuale sono descritte le procedure per l’acquisizione del certificato e le regole per l’utilizzo del servizio.

alfresco